1. Field of the Invention
The present invention relates generally to network switches and, more particularly, to a system and method for efficient buffer management for banked shared memory designs.
2. Introduction
Increasing demands are being placed upon the data communications infrastructure. These increasing demands are driven by various factors, including the increasing bandwidth requirements of Internet multimedia applications (e.g., distribution of news, financial data, software, video, audio and multi-person conferencing, etc). To accommodate the increasing bandwidth requirements, communication link speeds have also continued to evolve. For example, 10 Gigabit Ethernet (GbE) ports are commonly used for I/O on many of today's network switches.
Shared memory is commonly used to build output queued (OQ) switches. An OQ switch is known to maximize throughput, minimize delay and can offer quality of service (QoS) guarantees. Shared memory switches are not believed to scale well to high-capacity switches, however, because the requirements on the memory size, memory bandwidth and memory access time increase linearly with the line rate R and the number of ports N. For example, an N-port switch would need to operate N times faster than the line rate to achieve full throughput.
Consider, for example, a 128×10 Gbps switch. Here, a packet arrival rate using 10 Gbps for 64 bytes along with a 20 byte interpacket gap (IPG) is approximately 67 ns. The memory would therefore be required to perform a read and write in approximately 67 ns. For a 128 port 10 Gbps switch, the memory would be required to support all reads and writes in the time required to receive a single 65 byte packet. Thus, an access time of 67 ns/(128 reads+128 writes)=approximately 250 ps. As would be appreciated, a 250 ps access time is not practical for the technology of today's switches.
For this reason, development of high-capacity switches is moving towards banks of memories for scalability. With multiple banks of shared memories, bandwidth requirements can be evenly distributed across multiple memories, thereby increasing the memory access time required. For example, the average memory bandwidth required for unicast traffic is reduced by 1/m, where m is the number of memories.